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Computer Organization
Lecture 1
L 1.1 Intro (29:22)
L1.2 Intro 2 (12:28)
L1.3 Cache Size (17:03)
L1.4 Block Size (18:09)
L1.5 Cache Block (12:36)
L1.6 Write,Rep,Placement (12:14)
Homework Solutions
Quiz on Lecture 1
Lecture 2
L2.1 DM Cache (23:17)
L2.2 DMarchitecture (12:59)
L2.3 FullySetAssoc (8:22)
L2.4 SetAssoc (12:05)
L2.5 Miss and AMD (15:31)
L2.6 Addressing Modes (21:38)
Homework Solutions
Quiz on Lecture 2
Lecture 3
L3.1 Pipeline (11:50)
L3.2 UnderstatndingPipelining1 (15:19)
L3.3 UnderstandingPipeline2 (17:10)
L3.4 PipelineModes (15:19)
L3.5 Hazards (14:31)
L3.6 MechToOvercomeHazard (26:21)
Homework Solutions
Quiz on Lecture 3
Lecture 4
L4.1 PenaltyDataHzDependency (15:56)
L4.2 Mech(control,structural)Hazard (19:19)
Homework Solutions
Quiz on Lecture 4
Lecture 5
L5.1 IOInterfacePolling (15:12)
L5.2 InttDrivenIO (12:35)
L5.3 DMA (24:07)
L5.4 MultipleIOModule (12:59)
L5.5 MemoOrg (20:34)
L5.6 LargeMemoryDesign (7:18)
L5.7 TypesCharacMemo (7:43)
Homework Solutions
Quiz on Lecture 5
Lecture 6
L6.1 MicroProg (14:16)
L6.2 ControlWord (14:12)
L6.3 TypesMicroProg (7:52)
Homework Solutions
Quiz on Lecture 6
Subject Test
Full subject Quiz
GATE Previous Year Questions
GATE 2015 set-2 Q31 Cache Hit Miss (0:56)
GATE 2015 set-2 Q33 Pipeline (2:07)
GATE 2015 set-3 Q35 Dependency (1:31)
GATE 2015 set-1 Q29 Pipeline Speedup (1:14)
GATE 2015 set-1 Q28 Inst. Format (0:32)
GATE 2015 set-1 Q30 Disk Calc (1:48)
GATE 2017 set-1 Q11 Cache Misses (1:11)
GATE 2017 set-1 Q15 DM + Set Assoc (1:25)
GATE 2017 set-1 Q12 Adressing Modes (1:06)
GATE 2017 set-1 Q10 Adressing Modes (1:34)
GATE 2016 set-2 Q27 Cache Hit Miss (2:28)
GATE 2016 set-2 Q25 Set Assoc (1:00)
GATE 2017 set-1 Q14 Set Assoc (3:35)
GATE 2016 set-2 Q26 Pipeline (2:01)
GATE 2016 set-1 Q19 Basic size of adrs bus (1:00)
GATE 2016 set-2 Q24 Inst Size (1:28)
GATE 2019 Q2 Fully Assoc (0:36)
GATE 2015 set-2 Q32 Basic Intro (1:32)
GATE 2016 set-2 Q23 Basic Computation (2:42)
GATE 2016 set-1 Q20 DMA (1:06)
GATE 2017 set-2 Q16 Cache Miss Rate (2:43)
GATE 2019 Q3 Simple CC Calculation (2:35)
GATE 2017 set-2 Q18 EAT hitmiss tree (2:47)
GATE 2018 Q9 Pipeline (1:26)
GATE 2018 Q4 RISC Prop. (0:34)
GATE 2019 Q1 DRAM chip (1:28)
GATE 2018 Q5 DRAM chip (3:47)
GATE 2018 Q6 Intt. Routine (0:48)
GATE 2018 Q8 Category Type Inst. (2:54)
GATE 2016 set-2 Q22 Inst Size (0:47)
GATE 2017 set-2 Q17 DM cache (0:27)
GATE 2016 set-1 Q21 Pipeline Throughput (1:06)
GATE 2017 set-1 Q13 Pipeline Speedup (1:53)
GATE 2018 Q7 Set Assoc (3:07)
L4.2 Mech(control,structural)Hazard
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